In an electronic system, subsystems communicate with one another by transferring data among them in order to maintain the normal operation of the whole system. Almost all the modern electronic systems have sequential circuits that require an input clock for these systems to function properly. The source of the input clock for each subsystem may or may not be the same.
When data or a signal is transmitted from one subsystem to another subsystem, the transferred signal and the input clock entering the receiving subsystem usually have to comply with some requirements in timing. For example, these signals must be aligned when they arrive at the receiving subsystem. The relationship in timing is specified in the datasheet of various subsystems such as DRAM specification or PCI bus specification.
With reference to FIG. 1, a conventional electronic system with two subsystems is illustrated. A clock generator 100 provides clock inputs CK1 and CK2 to a first subsystem 101 and a second subsystem 102 respectively. As shown in FIG. 1, the two clock inputs CK1 and CK2 have different paths in the system. In the electronic system, data are transferred from the first subsystem 101 to the second subsystem 102.
Because of the path difference, some environmental factors may affect the timing relationship between CK1 and CK2. For example, the trace length of the clock input CK1 to the first subsystem 101 may be longer than the trace length of the clock input CK2. The signal driving capability of the first subsystem 101 can also be different from that of the clock generator 100, and the leaving time of the clock input from the clock generator 100 may be different from that of the data sent from the first subsystem 101 to the second subsystem 102. Consequently, CK1 has a clock skew with respect to CK2 as illustrated in FIG. 2. When the second subsystem samples the transferred data, incorrect data may be received as a result of the skew.
In general, there are two important timing requirements to be met in the clock and data signals of an electronic system. One is setup time and the other is hold time. Two possible data transactions with output delays are shown in FIG. 2, i.e., Data with output delay I and Data with output delay II, respectively. While one meets both setup and hold time requirement, the other violates the timing requirement.
How to satisfy the timing requirement plays an important role in designing modern electronic systems. In a computer system, increasing operation frequency is an effective approach to providing more operation power and higher performance. As the higher operation frequency is used and a cycle time is shortened, it becomes more and more difficult to meet the AC conditions of signals transferred among the computer subsystems. The timing relationship between the input clock and the transferred data is one of the AC conditions that have to be satisfied.